1. Field of the Invention
This invention relates to cell addressable arrays such as memory arrays and, more particularly, to such arrays which are capable of substituting good cells for defective cells without affecting the normal external addressing of the array.
2. Description of the Prior Art
Cell addressable arrays are well known in the art. For example, bit addressable random access memory arrays implemented in both bipolar and metal-insulator-semiconductor devices have been functionally organized on, for example, a single semiconductor chip with its own decoders and input/output logic and overhead circuitry. See U.S. Pat. No. 3,436,738 for an example of a bit addressable bipolar memory array and U.S. Pat. No. 3,740,731 for an example of a bit addressable MOS memory array, each assigned to the assignee of the present invention. See also U.S. Pat. No. 3,765,003 for another example of an MOS bit addressable random access memory. Array processors are described in U.S. Pat. No. 3,757,308.
Defect-tolerant memory systems have been suggested in the prior art in which a whole redundant row or column of cells is substituted for a selected row or column containing one or more defective cells. Consider, for example, U.S. Pat. No. 3,633,175 which describes a word addressable memory array incorporating a plurality of redundant rows which may be substituted for defective rows of cells by storing the word address of each defective row in a content addressable memory along with the address of a respective one of the redundant rows. Other examples of word addressable memories utilizing redundant word locations which may be substituted for defective word locations in the primary memory include U.S. Pat. Nos. 3,311,887; 3,331,058; and 3,422,402.
The defect-tolerant memory system of U.S. Pat. Nos. 3,753,244 and 3,753,235 include a cell addressable array with an extra line of cells on the chip together with a defective word address store and a comparator circuit for disabling a defective line of cells and replacing it with the extra lines of cells. In U.S. Pat. No. 3,753,244, the address is stored by selectively open-circuiting wire links of a read-only memory while in U.S. Pat. No. 3,753,235, wires are bonded to selectively ground bits of the read-only memory to store the defective addresses.
A similar defect-tolerant memory system is described in U.S. Pat. No. 3,755,791 in which the defective address store is electrically programmable and utilizes nonvolatile MNOS semiconductor devices arranged in a cross-coupled configuration. Again, in each of these examples, a single superfluous row or column is provided and only the row or column address is applied to the defective address store to switch the input address from the defective row or column to the redundant row or column. See also U.S. Pat. Nos. 3,714,637; 3,644,899; 3,738,761; 3,781,826; 3,772,652; 3,765,001; and 3,735,368 for other examples of address translation logic which permits a monolithic memory to utilize defective storage cells.
A still further example of a prior art defect-tolerant memory system is described in U.S. Pat. No. 3,659,275 in which a word addressable read-only memory having permanently stored words of data therein is accessed in parallel with a word location in a redundant memory. The words of data from the redundant memory contain at least one tag bit which determines whether the data from the read-only memory or from the redundant memory element is to be provided at the output terminals of the memory system.
As can be seen from the above discussion of the prior art, in each example, whether the memory be of the word addressable or cell addressable type, a requirement thereof is that at least one redundant line of cells be provided for each row or column in which one or more bad cells exist and that faulty bit locations of a memory array can only be tolerated to the extent that rows or columns in which such faulty locations exist do not exceed the total number of superfluous lines provided.